This application claims priority to Korean Patent Application No. 2004-113178, filed Dec. 27, 2004, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a raised cell landing pad and a method of fabricating the same.
2. Description of the Related Art
A semiconductor device, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a nonvolatile memory (NVM), may include a plurality of transistors. As a result of increased integration density of the semiconductor device, a gate electrode and source and drain regions which are components of the transistor have been miniaturized. For example, in case of the DRAM, a method of connecting a cell capacitor with a cell transistor to form a unit cell is widely employed. In order to increase integration efficiency, the cell transistor may be formed on a semiconductor substrate, an interlayer insulating layer may be formed thereon, and a cell capacitor may be formed on the interlayer insulating layer. The source region of the cell transistor may be connected to a lower electrode of the cell capacitor, the drain region of the cell transistor may be connected to a bit line, and the gate electrode of the cell transistor may be connected to a word line. As a cell transistor is miniaturized, it is very difficult to arrange interconnecting wirings.
FIG. 1 is a partial cross-sectional view of a conventional transistor including a landing pad. Referring to FIG. 1, the conventional transistor may include an isolation layer 13 which may be formed in a semiconductor substrate 11 and define an active region 15. Gate electrodes 17 may traverse the active region 15. As shown in FIG. 1, gate dielectric layers 16 may be interposed between the gate electrodes 17 and the active region 15. Hard mask patterns 18 may be laminated on the gate electrodes 17. Insulating spacers 19 may be formed on the sidewalls of the gate electrodes 17 and the hard mask patterns 18. Source and drain regions 23 may be formed in the active region 15 at both sides of the gate electrodes 17. Low concentration impurity regions 25 may reside in the active region 15 below insulating spacers 19. A first interlayer insulating layer 21 which covers the entire surface of the semiconductor substrate 11 having the gate electrodes 17 may be provided. Landing pads 27 which pass through the first interlayer insulating layer 21 and are electrically connected to the source and drain regions 23 may be provided. A second interlayer insulating layer 31 may be laminated on the first interlayer insulating layer 21 having the landing pads 27. A bit line 35 may be arranged on the second interlayer insulating layer 31 and electrically connected to any one of the source and drain regions 23 through a contact plug passing through the second interlayer insulating layer 31. A third interlayer insulating layer 41 covering the bit line 35 and the second interlayer insulating layer 31 may be laminated. Source contact plugs 45 which pass through the third interlayer insulating layer 41 and the second interlayer insulating layer 31 and are electrically connected to the landing pads 27 may be provided.
The upper surfaces of the landing pads 27 and the first interlayer insulating layer 21 may be arranged on a substantially same plane. Accordingly, it is difficult to ensure appropriate arrangement spacing around the source contact plugs 45. As shown in FIG. 1, although only a slight alignment error M is generated when forming the source contact plugs 45, the source contact plug may contact with the adjacent landing pad 27.